The invention relates to new and useful improvements in phase-locked-loops, and more particularly to such phase-locked-loops used in radio frequency systems.
Phase-locked-loops (PLL) are commonly used in radio frequency circuits to produce a precise, stable frequency. The basic elements of a PLL include a voltage controlled oscillator (VCO) for producing an output signal having a controlled frequency; a feedback loop containing a frequency divider; a phase detector for comparing the phase of the frequency-divided VCO output signal with that of a predetermined, stable frequency standard and producing an error signal representing the detected phase difference; a reference divider; and a loop filter for filtering the error signal and coupling it to the VCO to controllably adjust the output signal's frequency.
One of the problems inherent in PLL's is slow "lock-in" when a new frequency is selected. When the frequency is changed as is commonly done by changing the divisor in the loop frequency divider, the phase detector is presented a phase difference which must be resolved by changing the frequency of the VCO. The PLL does so by incrementally changing its frequency until the phase error at the phase detector is eliminated and a new stable frequency output is attained. Depending upon the design of the VCO, the component values in the loop filter, and the frequency of operation, this can take anywhere from parts of a second to several minutes. While this lock-in delay can be worked around in some applications, even though undesirable, it is totally unacceptable in other applications. A number of approaches have been tried to reduce the lock-in time, but to date none has proven to be adequate.
It is therefore an object of the present invention to provide a phase-locked-loop having a significantly reduced lock-in delay.